IC Test and Burn Sockets
In recent years, the IC industry has experienced an increase in electrostatic discharge (ESD)-induced failures. All process platforms are affected: microprocessors, chipsets and flash drives. Contactor materials have proven to be a major contributor to the failures.
After their production and packaging, microchips are tested in IC test and burn sockets. The aim of these sockets is to test the quality of the chips and their signal integrity. To control the specifications of the chips, sockets are continuously loaded, transported and unloaded during the testing phases. These movements can lead to an accumulation of electrical charges and therefore to ESD problems. Studies have shown that socket material interaction (tribo charging) with the chip was the main contributor to charge build-up on the device that led to the ESD damage. And predictably, ESD sensitivity is bound to increase as chip technology evolves in design and complexity.
IC test and burn sockets have antistatic, cleanliness and dimensional stability specifications. The sockets also have to resist thermal shocks and vibrations. The typical resins used are high temperature resins such as nylon, epoxy, ceramic, PCT, PEEK and SPS.
Requirements for the IC sockets include:
Static dissipative: (10^5-10^9 Ohms/cm^2)
Be dimensional stable for pitches below 1.0mm (low coefficient of thermal expansion (CTE), low water absorption % (<.25 24 hour percentage)
Compound must keep its static dissipative properties after molding
Provide a cost-effective solution
The last generation of chips had pitches of 0 mm, 3-0 mm and 4 mm; pitches are expected to decrease even more in the coming years. According to the International Technology Roadmap for Semiconductors (ITRS 2007), the MPU printed gate length is expected to decrease from 38 nanometers in 2008 to 17 nanometers in 2015, and to 5 nanometers in 2021.
This expected decrease in pitch will cause microchips to become much more sensitive to static discharge. In this context, IC test sockets manufacturers must respond quickly to this trend towards ultra-fine pitches by intensifying the IC integration and plastics engineering know-how.
To help the industry meet these more stringent requirements, Nanocyl Carbon Nanotubes have recently been incorporated into IC test and burn sockets.
Advantages of CNTs
Control of electrical conductivity. Because of CNTs’ nano-size, the electrical conductivity can be precisely controlled. Molders, for example, can eliminate the risk of hot spots (residual voltage) on the surface of the socket. In addition, carbon nanotubes compounds can provide the necessary static decay without increasing the conductivity too much. In fact, if static decay materials become too conductive, devices can deteriorate because the undesired signal can induce a deterioration of another circuit.
Retention of mechanical properties. Thanks to CNTs’ high electrical conductivity, fewer nanotubes are needed to impart the conductivity to the plastic parts. In fact, carbon nanotubes sockets have better toughness and elongation at break.
Dimensional stability. Besides other molding factors, molecular and fiber orientation and temperature variations can lead to part shrinkage. This property is crucial in sockets where pitches sometimes measure 1.0 mm or less.
High cleanliness. Many tests have been made on Nanocyl Carbon Nanotubes-injected parts. The results from the Ultrasonic Liquid Particle Count (LPC) show the presence of these particles. Less outgassing, ionic contamination and sloughing in abrasion testing have also been observed. For more information, see these test results at Nanocyl Carbon Nanotube Cleanliness Results